1. Field of the Invention
The present invention relates to the field of three-dimensional integrated circuits and more particularly to the fabrication of three-dimensional integrated circuits using direct wafer bonding.
2. Description of the Related Art
Semiconductor integrated circuits (ICs) are typically fabricated into and on the surface of a silicon wafer resulting in an IC area that must increase as the size of the IC increases. Continual improvement in reducing the size of transistors in ICs, commonly referred to as Moore's Law, has allowed a substantial increase in the number of transistors in a given IC area. However, in spite of this increased transistor density, a continual demand in increased IC complexity and functionality has resulted in a continued increase in IC chip area. This increase in chip area results in a reduction in chip yield and, correspondingly, increased chip cost.
Another trend in IC fabrication has been to increase the number of different types of circuits within a single IC, more commonly referred to as a System-on a-Chip (SoC). This fabrication typically requires an increase in the number of mask levels to make the different types of circuits and an increase in IC area to accommodate the increased number of types of circuits. This increase in mask levels and IC area also result in a reduction in yield, and correspondingly, increased chip cost.
An approach to avoiding this undesired decrease in yield and increase in cost is to vertically stack and subsequently interconnect ICs. These ICs can be of different size, come from different size wafers, comprise different functions (i.e., analog, digital, optical), be made of different materials (i.e., silicon, GaAs, InP, etc.). The ICs can be tested before stacking to allow Known Good Die (KGD) to be combined to improve yield. The success of this stack first, interconnect second approach depends on the yield and cost of the stacking and interconnection being favorable compared to the yield and cost associated with the increased IC area or SoC. A generic method for realizing this approach is to stack ICs using direct bonding and to interconnect ICs using conventional wafer thinning, photolithography masking, via etching, and interconnect metallization.
The cost of the interconnect portion of this approach is directly related to the number of photolithography masking levels required to etch vias and form electrical interconnects. It is thus desirable to minimize the number of photolithography masking levels required to etch vias and form electrical interconnects.
One version of vertical stacking and interconnection is where ICs (on a substrate) are bonded face-to-face, or IC-side to IC-side. This version is typically done in a die-to-wafer format where die are bonded IC-side down, to a wafer IC-side up. In this format, after bonding, the die are typically substantially thinned by removing most of the die substrate. The die substrate can not, in general, be totally removed due to the location of transistors in the substrate. The substrate is thus typically removed to the greatest extent practicable, leaving sufficient residual substrate to avoid damage to the transistors. An interconnection to the die IC is then preferably made by etching a via through the remaining substrate to an interconnection location in the die IC, such that there are no necessary transistors in the vicinity of this via. It is furthermore preferable, in order to achieve the highest interconnection density, to continue this via through the entire die-IC and into the wafer-IC to an interconnection location in the wafer IC. This via typically extends through an insulating dielectric material that provides desired electrical isolation from interconnection locations in the die IC and wafer IC. After the formation of this via, it is typically necessary to interconnect the interconnection location in the die-IC with the interconnection location in the wafer-IC. This is preferably done with a conductive material on an insulating layer between the conductive material and the exposed substrate on the via sidewall to avoid undesired electrical conduction between the conductive material and the substrate.
The fabrication of this structure typically takes four photolithography masking levels to build. These levels are 1) via etch through substrate, 2) via etch through insulating dielectric material in the die IC and wafer IC that exposes desired conductive material in the die IC and wafer IC, 3) via etch through the insulating layer that electrically isolates the conductive material that interconnects the interconnect location in the die IC with the interconnect location in the wafer IC to the exposed substrate via sidewall that exposes desired conductive material in the die IC and wafer IC, 4) interconnection with conductive material between exposed interconnection point in the die IC with exposed interconnection point in the wafer IC.
The patterns defining the via etching through the insulating (dielectric) material(s) are typically smaller than the pattern defining the via etch through the substrate to adequately expose the interconnection points in the die IC and wafer IC and to avoid removing insulating material on the substrate via sidewall. Since these patterns are formed after the via in the substrate, this patterning is typically done at a lower topographical level that the patterning of the substrate via. This results in a patterning over a non-planar structure that limits the scaling of the structure to very small feature size that is desirable to achieve the highest interconnection density and consumes the least possible silicon substrate where functional transistors would otherwise reside.
It is thus desirable to have a device that comprises a structure and a method to fabricate the structure requiring a reduced number of masking steps and masking steps that can be realized on a planar surface, at the highest, or one of the highest, levels of topography in the structure.